FPGA ISE MAP错误，求助！！

你是不是把普通IO口的信号，用成全局时钟信号了？

这样肯定是错误的。

FPGA有专用的时钟管脚输入，你代码得优化优化才行了，否则跑不了高速……

使用ISE14.5在spartan6 LX9 TQG144上写电路，其中有一段这样的描述被MAP时报错：reg CISCLK_pre = 1'b0; reg CISCLK_now = 1'b0; wire CISCLK_pulse; always@(posedge vsmp_CLK) begin CISCLK_now <= CIS_inclk; CISCLK_pre <= CISCLK_now; end assign CISCLK_pulse = (!CISCLK_now)&&(CISCLK_pre);报错信息如下：ERROR:Place:1136 - This design contains a global buffer instance,, driving the net,, that is driving the following (first 30) non-clock load pins. < PIN: CIS_ADC_TopModule_INST/ADC_Controller_INST/VSMP_OEB_INST/CISCLK_now.D; > < PIN: FIFO_Top_Module_STAN/DATA_Recieved_Module_STAN/CIS_Signal_Edge/Signal_Edge_no w.D; > This is not a recommended design practice in Spartan-6 due to limitations in the global routing that may cause excessive delay, skew or unroutable situations. It is recommended to only use a BUFG resource to drive clock loads. If you wish to override this recommendation, you may use the CLOCK_DEDICATED_ROUTE constraint (given below) in the .ucf file to demote this message to a WARNING and allow your design to continue. < PIN "CLK_Module_INST/BUFGMUX_CIS_INST.O" CLOCK_DEDICATED_ROUTE = FALSE; >ERROR:Pack:1654 - The timing-driven placement phase encountered an error.