用VHDL语言设计7段数码管动态显示08210511这8个数

第一部分library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;entity dis_08210511 is
port( clk:in std_logic;
rst:in std_logic;
dis:out std_logic_vector(6 downto 0)
);
end dis_08210511;architecture Behavioral of dis_08210511 iscomponent decode
port(putin :in integer range 0 to 9 ;
output: out std_logic_vector(6 downto 0)
);
end component;
signal disnum0,disnum1,disnum2,disnum3,disnum4,disnum5,disnum6,disnum7:integer;
signal tmp:integer range 1 to 16 :=1;
signal outnum: integer:=0;
begin
disnum0<=0;disnum1<=8;disnum2<=2;disnum3<=1;disnum4<=0;disnum5<=5;disnum6<=1;disnum7<=1;
u1:decode port map (outnum,dis);
u2:process(clk)
begin
if clk'event and clk='1' then
if rst='1' then
tmp<=1;
elsif tmp=16 then
tmp<=1;
else
tmp<=tmp+1;
end if;
case tmp is
when 1 =>outnum<=disnum0;
when 3 =>outnum<=disnum1;
when 5 =>outnum<=disnum2;
when 7 =>outnum<=disnum3;
when 9 =>outnum<=disnum4;
when 11 =>outnum<=disnum5;
when 13 =>outnum<=disnum6;
when 15 =>outnum<=disnum7;
when others=> null;
end case;
end if;
end process;
end Behavioral;--第二部分：library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity mult8 is
port(pwm_enable,reset_n,clk:in std_logic;
pwm_out:out std_logic);
end entity;
architecture eqample of mult8 is
begin
process(clk,reset_n)
begin
if(reset_n='0')then
pwm_out<='0';
else
if(clk'event and clk='1')then
if(pwm_enable='1')then
pwm_out<='1';
else
pwm_out<='0';
end if;
else
pwm_out<='0';
end if;
end if;
end process;
end eqample;