用VHDL语言编（共八个）七段数码管的随机显示程序

我这里有一个自己弄的现成的程序。可以给你看看。
首先是你要有数码管译码器，以下这个是共阴数码管的译码电路的VHDL。segin是输入的你要显示的二进制数据，比如1001代表的就是9。seg就是输出的点亮七段数码管的信号。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity seg is
port(
segin :in std_logic_vector(3 downto 0);
seg :out std_logic_vector(7 downto 0)
);
end entity seg;

architecture a of seg is

begin
process(segin)
begin
case segin is
when "0000" => seg <= "01111110";
when "0001" => seg <= "00001100";
when "0010" => seg <= "10110110";
when "0011" => seg <= "10011110";
when "0100" => seg <= "11001100";
when "0101" => seg <= "11011010";
when "0110" => seg <= "11111010";
when "0111" => seg <= "00001110";
when "1000" => seg <= "11111110";
when "1001" => seg <= "11011110";
when others => seg <= "01111110";
end case;
end process;
end a;

如果有三位要显示的话，那么只要三个数据分别输入三个译码电路，然后输出的就是你三位分别需要的驱动信号了。接下来就是你如何将这三个LED分别选通，由于三根数码管是串联的，所以如果不加片选信号，三根应该显示同一个数字。我们只要在一个时间段里面显示一位，即片选一位，然后将这一位所对应的数字输出，另外两个不亮。接着立马更换显示第二位，然后是第三位，只要频率够快就可以了。下面给出片选信号输出的VHDL。

其中Clk为时钟信号，每次时钟上升沿做一次选通变换，seg1，2，3分别为三位输入的数码管驱动信号，seg为输出的数码管输出信号，en为三位的选通输出信号，0电平点亮。

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity xt is
port(
clk :in std_logic;
seg1 :in std_logic_vector(7 downto 0);
seg2 :in std_logic_vector(7 downto 0);
seg3 :in std_logic_vector(7 downto 0);
seg :out std_logic_vector(7 downto 0);
en :out std_logic_vector(2 downto 0)
);
end entity xt;

architecture a of xt is
signal counter: integer range 0 to 3;

begin
p1: process
begin
wait until clk='1';
if counter=2 then
counter<=0;
else
counter<=counter+1;
end if;
end process;

p2:process(counter)
begin
case counter is
when 0 => seg <= seg1;en<="011";
when 1 => seg <= seg2;en<="101";
when others => seg <= seg3;en<="110";

end case;
end process;
end a;

如果还有疑问的可以再提。

我了解了，我可以帮你做好发到你邮箱