用VHDL源程序设计一个带同步置数和同步清零端的100进制计数器，要求以十六进制输出。

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity count_100 is
port(clk,reset:in std_logic;
load:in std_logic;
current_vaule:in std_logic_vector(6 downto 0);
outdata:out std_logic_vector(6 downto 0));
end entity;
architecture art of count_100 is
begin
process(clk,reset,load,current_vaule)
variable cnt:std_logic_vector(6 downto 0);
begin
if reset='1' then
cnt:="0000000";
elsif clk'event and clk='1' then
if load='1' then
cnt:=current_vaule;
elsif cnt="1100100" then
cnt:="0000000";
else cnt:=cnt+1;
end if;
end if;
outdata<=cnt;
end process;
end art;