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在Verilog中仿真中，输出的结果都是不确定元素XXXX,我设置了一个时钟信号clk,为什么仿真失败，如何改正？
在Verilog中仿真中，输出的结果都是不确定元素XXXX,我设置了一个时钟信号clk,为什么仿真失败，如何改正？
2025-03-16 10:48:33
推荐回答（1个）
回答1：
你没发现连CLK都是红的么？说明CLK就不对...把clk前面的assign换成always，定义改成reg
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