用VHDL语言编写八选一数据选择器程序

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mux8 IS
PORT(a,b,c,i0,i1,i2,i3,i4,i5,i6,i7: IN STD_LOGIC;
q: OUT STD_LOGIC);
END mux8;
ARCHITECTURE behave OF mux8 IS
SIGNAL sel: STD_LOGIC_VECTOR (2 DOWNTO 0);
BEGIN
sel<=a&b&c;
PROCESS (sel,i0,i1,i2,i3,i4,i5,i6,i7)
BEGIN
CASE sel IS
WHEN "000" =>q<=i0;
WHEN "001" =>q<=i1;
WHEN "010" =>q<=i2;
WHEN "011" =>q<=i3;
WHEN "100" =>q<=i4;
WHEN "101" =>q<=i5;
WHEN "110" =>q<=i6;
WHEN "111" =>q<=i7;
WHEN OTHERS=>q<='X'; --必须大写（强未知）仿真时有意义，综合时忽略
END CASE;
END PROCESS;
END behave;

LIBRARY
IEEE;
USE
IEEE.STD_LOGIC_1164.ALL;
ENTITY
mux8
IS
PORT(a,b,c,i0,i1,i2,i3,i4,i5,i6,i7:
IN
STD_LOGIC;
q:
OUT
STD_LOGIC);
END
mux8;
ARCHITECTURE
behave
OF
mux8
IS
SIGNAL
sel:
STD_LOGIC_VECTOR
(2
DOWNTO
0);
BEGIN
sel<=a&b&c;
PROCESS
(sel,i0,i1,i2,i3,i4,i5,i6,i7)
BEGIN
CASE
sel
IS
WHEN
"000"
=>q<=i0;
WHEN
"001"
=>q<=i1;
WHEN
"010"
=>q<=i2;
WHEN
"011"
=>q<=i3;
WHEN
"100"
=>q<=i4;
WHEN
"101"
=>q<=i5;
WHEN
"110"
=>q<=i6;
WHEN
"111"
=>q<=i7;
WHEN
OTHERS=>q<='X';
--必须大写（强未知）仿真时有意义，综合时忽略
END
CASE;
END
PROCESS;
END
behave;