EDA数字钟设计

1.Topclock（元件例化 顶层文件）
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all;
Use ieee.std_logic_unsigned.all;
Entity topclock is
Port(clk,clr,en,m1,h1:in std_logic;
alarm:out std_logic;
secs,secg,mins,ming,hours,hourg:buffer std_logic_vector(3 downto 0));
End;
2. 秒模块程序
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity SECOND is
port(clk,clr:in std_logic;
sec1,sec0:out std_logic_vector(3 downto 0);
co:out std_logic);
end SECOND;

architecture SEC of SECOND is
begin
process(clk,clr)
variable cnt1,cnt0:std_logic_vector(3 downto 0);
begin
if clr='1' then
cnt1:="0000";
cnt0:="0000";
elsif clk'event and clk='1' then
if cnt1="0101" and cnt0="1000" then
co<='1';
cnt0:="1001";
elsif cnt0<"1001" then
cnt0:=cnt0+1;
else
cnt0:="0000";

if cnt1<"0101" then
cnt1:=cnt1+1;
else
cnt1:="0000";
co<='0';
end if;
end if;
end if;
sec1<=cnt1;
sec0<=cnt0;

end process;
end SEC;

3.分模块程序
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity MINUTE is
port(clk,en:in std_logic;
min1,min0:out std_logic_vector(3 downto 0);
co:out std_logic);
end MINUTE;

architecture MIN of MINUTE is
begin
process(clk)
variable cnt1,cnt0:std_logic_vector(3 downto 0);
begin
if clk'event and clk='1' then
if en='1' then
if cnt1="0101" and cnt0="1000" then
co<='1';
cnt0:="1001";
elsif cnt0<"1001" then
cnt0:=cnt0+1;
else
cnt0:="0000";

if cnt1<"0101" then
cnt1:=cnt1+1;
else
cnt1:="0000";
co<='0';
end if;
end if;
end if;
end if;
min1<=cnt1;
min0<=cnt0;

end process;
end MIN;

4.时模块程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity HOUR is
port(clk,en:in std_logic;
h1,h0:out std_logic_vector(3 downto 0));
end HOUR;

architecture hour_arc of HOUR is
begin
process(clk)
variable cnt1,cnt0:std_logic_vector(3 downto 0);
begin
if clk'event and clk='1' then
if en='1' then
if cnt1="0010" and cnt0="0011" then
cnt1:="0000";
cnt0:="0000";
elsif cnt0<"1001" then
cnt0:=cnt0+1;
end if;
end if;
end if;
h1<=cnt1;
h0<=cnt0;

end process;
end hour_arc;

----5.扫描模块程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity SELTIME is
port(
clk:in std_logic;
sec1,sec0,min1,min0,h1,h0:in std_logic_vector(3 downto 0);
daout:out std_logic_vector(3 downto 0);
sel:out std_logic_vector(2 downto 0));
end SELTIME;
architecture fun of SELTIME is
signal count:std_logic_vector(2 downto 0);
begin
sel<=count;
process(clk)
begin
if(clk'event and clk='1') then
if(count>="101") then
count<="000";
else
count<=count+1;
end if;
end if;
case count is
when"000"=>daout<= sec0;
when"001"=>daout<= sec1;
when"010"=>daout<= min0;
when"011"=>daout<= min1;
when"100"=>daout<=h0;
when others =>daout<=h1;
end case;
end process;
end fun;

6.显示模块程序

library ieee;
use ieee.std_logic_1164.all;
entity DISPLAY is
port(d:in std_logic_vector(3 downto 0);
q:out std_logic_vector(6 downto 0));
end DISPLAY;
architecture disp_are of DISPLAY is
begin
process(d)
begin

case d is
when"0000" =>q<="0111111";
when"0001" =>q<="0000110";
when"0010" =>q<="1011011";
when"0011" =>q<="1001111";
when"0100" =>q<="1100110";
when"0101" =>q<="1101101";
when"0110" =>q<="1111101";
when"0111" =>q<="0100111";
when"1000" =>q<="1111111";
when others =>q<="1101111";
end case;
end process;
end disp_are;

-----7.定时闹钟模块程序

library ieee;
use ieee.std_logic_1164.all;
entity ALERT is
port(m1,m0,s1,s0:in std_logic_vector(3 downto 0);
clk:in std_logic;
q500,qlk:out std_logic);
end ALERT;

architecture sss_arc of ALERT is
begin
process(clk)
begin

if clk'event and clk='1' then
if m1="0101" and m0="1001" and s1="0101" then
if s0="0001" or s0="0011" or s0="0101" or s0="0111" then
q500<='1';
else
q500<='0';
end if;
end if;

if m1="0101" and m0="1001" and s1="0101" and s0="1001" then
qlk<='1';
else
qlk<='0';
end if;
end if;
end process;
end sss_arc;
Architecture one of topclock is
Component second1
Port( clks,clr:in std_logic;
secs,secg: buffer std_logic_vector(3 downto 0);
cout1: out std_logic);
End Component;
Component min1
Port(clkm,clr:in std_logic;
mins,ming:buffer std_logic_vector(3 downto 0);
enmin,alarm: out std_logic);
End Component;
Component hour1
Port(clkh,clr:in std_logic;
hours,hourg:buffer std_logic_vector(3 downto 0));
End Component;
Component madapt
Port(en,m1,clk,secin:in std_logic;
minset:out std_logic);
End Component;
Component hadapt
Port(en,h1,clk,minin:in std_logic;
hourset:out std_logic);
End Component;
signal a,b,c,d: std_logic;
begin
u1:second1 port map(clr=>clr,
secs=>secs,secg=>secg,clks=>clk, cout1=>a);
u2:min1 port map(clr=>clr,alarm=>alarm,
mins=>mins,ming=>ming,clkm=>b,enmin=>c);
u3:hour1 port map(clr=>clr,
hours=>hours,hourg=>hourg,clkh=>d);
u4:madapt port map(en=>en,m1=>m1,clk=>clk,secin=>a,minset=>b);
u5:hadapt port map(en=>en,h1=>h1,clk=>clk,minin=>c,hourset=>d);
end;
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