怎样用VHDL设计含有异步清零和同步时钟使能的16位加法计数器

这个很简单啊，每次时钟来+1就是了。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity count is
port
(
clk : in std_logic;
rst : in std_logic;
count_out : out std_logic_vector(15 downto 0)
);
end count;

architecture arc of count is
signal count : std_logic_vector(15 downto 0);

begin
process(clk,rst)
begin
if rst = '1' then
count <= (others=>'0');
elsif rising_edge(clk) then
count <= count + 1;
end if;
end process;
count_out <= count;

end arc;