library ieee;
use std_logic_1164.all;
entity temp is
port(a ：in std_logic;
b : in std_logic;
c:out std_logic;
d:out std_logic
);
end temp;
archiecture str of temp is
begin
c <= a and b;
d <=( a or b) and (not(a and b));
end str;
ENTITY and_or IS
PORT(A,B:IN bit; C,D:OUT bit);
END and_or;
ARCHITECTURE rtl OF and_or IS
BEGIN
C <= A AND B;
D <= A XOR B;
END rtl;
是个1位半加器。
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