数字钟vhdl设计中 扫描电路 出现错误！！！急急急！

改为：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY smdl IS
PORT (A,B,C,D,E,F:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S:out STD_LOGIC_VECTOR(2 DOWNTO 0);
y:out STD_LOGIC_VECTOR(6 DOWNTO 0);
CP:in std_logic);
END smdl;
ARCHITECTURE a OF smdl IS
signal Z : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS (CP)
VARIABLE SN: STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
IF CP'EVENT AND CP='1' then
IF SN="101" THEN
SN:="000";
ELSE
SN:=SN+1;
END IF;
CASE SN IS
WHEN"000"=>Z<=A;
WHEN"001"=>Z<=B;
WHEN"010"=>Z<=C;
WHEN"011"=>Z<=D;
WHEN"100"=>Z<=E;
WHEN"101"=>Z<=F;
WHEN OTHERS=>NULL;
END CASE;
END IF;
S<=SN;
END PROCESS;
PROCESS (z)
BEGIN
CASE Z IS
WHEN"0000"=>Y<="1111110";
WHEN"0001"=>Y<="0110000";
WHEN"0010"=>Y<="1101101";
WHEN"0011"=>Y<="1111001";
WHEN"0100"=>Y<="0110011";
WHEN"0101"=>Y<="1011011";
WHEN"0110"=>Y<="1011111";
WHEN"0111"=>Y<="1110000";
WHEN"1000"=>Y<="1111111";
WHEN"1001"=>Y<="1111011";
WHEN"1010"=>Y<="1111110";
WHEN"1011"=>Y<="0110000";
WHEN"1100"=>Y<="1101101";
WHEN"1101"=>Y<="1111001";
WHEN"1110"=>Y<="0110011";
WHEN"1111"=>Y<="1011011";
when others=>y<="1111111";
END CASE;
END PROCESS;
END a;