用verilog写一个8位循环移位器！！

module barrel_org(s,a_p,b_p);
input [2:0] s;
input [7:0] a_p;
input [7:] b_p;
reg [7:0] b_p;

always@(a_p or s)
begin
case(s)
3'b000:
begin
b_p <= a_p;
end

3'b001:
begin
b_p[7] <= a_p[0];
b_p[6:0] <= a_p[7:1];
end

3'b010:
begin
b_p[7:6] <= a_p[1:0];
b_p[5:0] <= a_p[7:2];
end

3'b011:
begin
b_p[7:5] <= a_p[2:0];
b_p[4:0] <= a_p[7:3];
end

3'b100:
begin
b_p[7:4] <= a_p[3:0];
b_p[3:0] <= a_p[7:4];
end

3'b101:
begin
b_p[7:3] <= a_p[4:0];
b_p[2:0] <= a_p[7:5];
end

3'b110:
begin
b_p[7:2] <= a_p[5:0];
b_p[1:0] <= a_p[7:6];
end

3'b111:
begin
b_p[7:1] <= a_p[6:0];
b_p[0] <= a_p[7];
end

default:
begin
b_p = a_p;
end

endcase
end
endmodule

always @(posedge clk)
begin
data<={data[6:0],data[7]};//循环左移

//data<={data[0],data[7:1]};//循环右移
end